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320x240 Pixel Chip using Dynamic Logic Circuits

Summary

We reduced transistors in the pixel circuit using dynamic logic and implemented 320x240 pixels in 9.22mm x 8.52 mm chip, This is the biggest size among vision chips that perform digital processing.

 

Reference

  1. Takashi Komuro, Atsushi Iwashita, Masatoshi Ishikawa: A QVGA-size Pixel-parallel Image Processor for 1,000-fps Vision, IEEE Micro, vol. 29 no. 6, pp. 58-67 (2009)
Ishikawa Senoo Laboratory, Department of Information Physics and Computing, Department of Creative Informatics,
Graduate School of Information Science and Technology, University of Tokyo
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