Interleaved Pixel Lookup


In this project, we try to parallelize pixel lookup operations in an embedded computer vision hardware. Implementation of pixel lookup, a conversion between geometry to pixel data, is a design bottleneck for embedded hardware. It usually requires a random access memory that takes large portion of hardware cost, consumes large power, while it is difficult to increase its throughput. For the efficient implementation, we focus on interleaving, a technique to parallelize memory operations successfully utilized in graphics hardwares. An FPGA implementation of Lucas-Kanade, one of the most basic image registration algorithms, showed that interleaving contributes to 16x times larger throughput than straightforward configuration with a single port memory without major increase in hardware cost.



  1. Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa: Interleaved Pixel Lookup for Embedded Computer Vision, Fourth IEEE Workshop on Embedded Computer Vision (ECVW) (Anchorage, 2008.6.28) / Proceedings. [Paper] [Slides]