masterhead masterhead  masterhead

A Programmable Vision Chip with 64x64 pixels

Summary

A programmable vision chip that integrates 64x64 pixels has been developed. It adopts newly designed dynamically reconfigurable SIMD architecture for processing circuits. It is fabricated using 0.35um CMOS process and the chip size is 5.4mm x 5.4mm. Each pixel area is 67.4um x 67.4um and 256x256 pixels could be integrated on about 1.8cm square chip.


Reference

  1. Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa: A Dynamically Reconfigurable SIMD Processor for a Vision Chip, IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, pp. 265-268 (2004) [PDF]
Ishikawa Senoo Laboratory, Department of Information Physics and Computing, Department of Creative Informatics,
Graduate School of Information Science and Technology, University of Tokyo
Ishikawa Senoo Laboratory WWW admin: www-admin@k2.t.u-tokyo.ac.jp
Copyright © 2008 Ishikawa Senoo Laboratory. All rights reserved.